We are seeking an experienced RTL ASIC Design Engineer to join our client’s semiconductor design team in Bangalore. The ideal candidate will have deep expertise in digital design, RTL development, and ASIC implementation flows, with a strong background in Verilog/SystemVerilog-based RTL design and hands-on experience working on complex SoC/ASIC projects from specification to tape-out.
Develop, verify, and optimize RTL code for high-performance ASIC designs.
Collaborate with architecture and verification teams to define specifications and micro-architectures.
Perform design synthesis, linting, CDC analysis, and timing closure.
Participate in design reviews and ensure functional correctness and design quality.
Work closely with backend teams for integration, simulation, and sign-off activities.
Debug design and verification issues to ensure reliable and efficient chip delivery.
Bachelor’s or Master’s degree in Electronics, Electrical, or related engineering field.
Minimum 9 years of experience in RTL Design and ASIC development.
Proficiency in Verilog/SystemVerilog and RTL coding best practices.
Strong understanding of digital design principles, SoC architecture, clocking, reset, and power domains.
Familiarity with EDA tools for lint, synthesis, and simulation (e.g., Synopsys, Cadence, Mentor).
Exposure to Design Verification environments and close collaboration with DV teams.
Excellent debugging, analytical, and problem-solving skills.
Strong communication and teamwork abilities.
Verilog, SystemVerilog, RTL Design, ASIC Design, SoC Architecture, Digital Design, Lint, CDC, Synthesis, Static Timing Analysis (STA), Low-Power Design, Simulation, EDA Tools, VLSI, Chip Design, Hardware Debugging