We are seeking an experienced Design Verification Engineer with a strong background in SystemVerilog (SV) and UVM methodologies. The ideal candidate will be responsible for verifying complex SoC and IP designs, developing robust verification environments, and ensuring high-quality deliverables. This is an exciting opportunity to work on PCIe-based designs and contribute to cutting-edge semiconductor solutions.
Develop, implement, and maintain UVM-based verification environments for complex digital designs.
Create test plans, test cases, and coverage models to validate design functionality.
Perform simulation, debugging, and regression analysis to identify and resolve design issues.
Collaborate closely with the RTL design team to understand design specifications and resolve verification challenges.
Analyze functional coverage reports and drive verification closure.
Work on interface protocols such as PCIe, ensuring compliance and performance validation.
Participate in code and test plan reviews, contributing to continuous improvement of verification processes.
Bachelor’s or Master’s degree in Electronics, Electrical, or Computer Engineering.
5+ years of experience in ASIC/SoC design verification.
Hands-on experience with SystemVerilog and UVM methodologies.
Strong understanding of PCIe protocol and related verification flows.
Proficient in simulation tools (e.g., VCS, QuestaSim, Xcelium).
Experience with coverage-driven and constrained-random verification.
Excellent debugging and problem-solving skills.
Strong communication and collaboration abilities.
PCIe, SystemVerilog (SV), UVM, SoC Verification, Functional Coverage, Constrained Random Testing, VCS, QuestaSim, Xcelium, Debugging, Regression Analysis, Test Planning