We are urgently seeking a highly skilled Analog Layout Engineer with strong experience in advanced lower technology nodes (2nm / 3nm / 5nm). The ideal candidate will be responsible for designing, implementing, and optimizing analog and mixed-signal layouts while ensuring compliance with DRC/LVS standards. This is a high-priority requirement for our client’s Hyderabad location — immediate joiners preferred.
Perform full-custom analog and mixed-signal layout design for advanced nodes (2nm/3nm/5nm).
Work closely with design and verification teams to ensure layout vs. schematic (LVS) and design rule check (DRC) compliance.
Handle floor planning, device placement, routing, parasitic extraction, and layout optimization.
Ensure high-quality, low-noise, and high-performance layout designs adhering to foundry specifications.
Collaborate with circuit designers and verification engineers to resolve layout-related issues during the tape-out process.
Conduct post-layout verification and assist in layout migration and reuse across technology nodes.
Maintain strong documentation and version control throughout the design cycle.
Experience: Minimum 5+ years in Analog Layout Design.
Proven expertise in lower nodes (2nm / 3nm / 5nm) — must have handled FinFET or advanced process nodes.
Strong knowledge of EDA tools (Virtuoso, Cadence, Mentor Graphics, Synopsys Custom Compiler, etc.).
Excellent understanding of analog building blocks — Op-Amps, Bandgaps, ADCs/DACs, PLLs, etc.
Experience with parasitic extraction, IR drop analysis, and electromigration checks.
Strong communication and collaboration skills with the ability to work in cross-functional design teams.
Location: Hyderabad
Mode of Interview: Face-to-Face (F2F)
Notice Period: Immediate joiners preferred
Analog Layout, Mixed-Signal Layout, 2nm, 3nm, 5nm, FinFET, DRC, LVS, Virtuoso, Cadence, EDA Tools, Parasitic Extraction, Floor Planning, Layout Optimization, Tape-Out, IR Drop Analysis, Electromigration, Bandgap, Op-Amp, ADC/DAC, PLL.